1. Field of the Invention
The present invention relates to a gate driving circuit of a display, and a method of fabricating a device of a display, and more particularly, to a pull-down module of a gate driver on array (GOA) having high pull-down ability, and a method of making a device of a display capable of avoiding metal loss.
2. Description of the Prior Art
FIG. 1 illustrates a circuit diagram of a gate driving circuit of a display. As shown in FIG. 1, the gate driving circuit is used to generate pulse signals according to a predetermined timing sequence, and the pulse signals are delivered to gate lines so as to control switching of the thin film transistors (TFTs) in the pixel regions of the display. The gate driving circuit mainly includes a plurality of signal lines (e.g. L1, L2, L3 and L4), and a plurality of TFTs (e.g. T1, T2, T3 and T4). The signal line L1 is used to deliver a voltage signal Vss, the signal line L2 is used to deliver a start pulse signal Vst, the signal line L3 is used to deliver a complementary clock signal Vxck, and the signal line L4 is used to deliver a clock signal Vck. The TFT T1 serves as a starting switch, and the TFT T2 serves as a pulse switch. When the start pulse signal Vst turns on the TFT T1, the TFT T2 is also turned on so that clock signal Vck can pass and provide a voltage signal VN to the Nth gate line of the display panel. The TFTs T3, T4 serve as a pull-down module, which pulls down the voltage of the signal delivered to the gate line to a reference voltage, i.e. the level of the voltage signal Vss, for example −6V. Specifically, the TFT T4 can pull down the voltage of the node Q1 to the level of the voltage signal Vss, and the TFT T3 can pull down the voltage of the node Q2 to the level of the voltage signal Vss.
The conventional TFTs T3, T4 cannot provide pull-down effect when turned off. However, the start pulse voltage Vst or the clock signal Vck may have abnormal waveform during this period of time, and consequently the TFTs of the pixel regions may be turned on falsely. Thus, the pull-down ability of the conventional pull-down module requires to be improved.
Also, in the conventional photolithography process of display fabrication, for example 4PEP array processes, the size of the metal pattern actually formed is usually found smaller than its original designed size. This is so called metal loss, and the metal loss problem is serious particularly in patterning the second metal layer (Metal 2). This metal loss problem influences the reliability of the TFTs of pixel regions, the TFTs of gate driver on array (GOA), and other components e.g. photo spacer stages.